The present invention relates to a process of fabricating a miniature MlSFET (metal-insulator-semiconductor field effect transistor) of a minute construction.
Miniaturization of MISFETs has been achieved by the law of scaling. According to this law, if the applied voltage and the physical dimensions are reduced to 1/K and the impurity concentration is increased to K times, the electric field configuration is unchanged, and the switching time and the current consumption are reduced to 1/K.sup.2. However in practice it is rare that the power supply voltage is reduced in proportion with the physical dimensions. This is because of the desirability of facilitating an interface with external circuits and providing adequate noise margins. As a result, the electric field in the MISFET is increased, and, because of the hot-carrier injection effect, the threshold voltage may be varied and the mutual conductance is lowered, so that the reliability of the device is degraded.
Various proposals have been made to alleviate the hot carrier injection effect. An example is the use of an LDD (lightly-doped drain) structure, as is disclosed in the lEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April 1982, pp. 590-596, "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", Tsang, et al. This LDDFET is described with reference to FIGS. 1A to 1F.
As illustrated in FIG. 1A, a silicon substrate 1 is prepared, on which a field oxide film 2, a gate oxide film 3, a polycrystalline silicon (poly-Si) film 4, and a CVDSiO.sub.2 film 5 formed by chemical vapor deposition) are formed in turn.
Next, as illustrated in FIG. 1B, the CVDSiO.sub.2 film 5 and the poly-Si film 4 are patterned. The patterned poly-Si film 4 constitutes a gate electrode.
Next, as illustrated in FIG. 1C, ion-implantation is performed using the patterned films 5 and 4 as a mask (i.e., by self-alignment) to form N- regions (lightly-doped regions) 6 in the silicon substrate 1.
Next, as illustrated in FIG. 1D, a CVDSiO.sub.2 film 7 is deposited over the entire surface.
Next, as illustrated in FIG. 1E, RIE (reactive ion etching) is performed to form sidewalls 8.
Next, as illustrated in FIG. 1F, ion implantation is performed using the patterned films 5 and 4, and the sidewalls 8 as a mask (i.e., by self alignment) to form N.sup.+ regions (heavily doped regions) 9.
Subsequently, an interlayer insulating film is deposited, and a contact is opened and an Al (aluminum) conductor layer 10 is formed to obtain an LDDFET as shown in FIG. 2.
In this way, the lightly-doped regions are formed under the sidewalls 8 to alleviate the electric field intensity.
The hot carrier injection effect of the MISFET of the above-described MISFET depends largely on the shape of the sidewalls 8 (FIG. 1E). Accordingly, the process of forming the sidewalls is critical. But it has been difficult to form sidewalls of a desirable shape.